1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
3D memory devices have been developed in a variety of configurations that include vertical channel structures. In vertical channel structures, memory cells including charge storage structures are disposed at interface regions between horizontal planes of conductive strips arranged as word lines, and vertical active strips including channels for the memory cells.
A memory device can include multiple planes of memory cells that includes an arrangement of multiple stacks of horizontal conductive strips, or word lines. The trend of increasing memory capacity tends to increase the number of stacks of horizontal conductive strips, which are selected by string select lines. Unfortunately, this increased number of stacks causes increased capacitance, noise, and power consumption.
One approach to increase memory capacity without just increasing the number of stacks of horizontal conductive strips, is to increase the number of planes and the number of staircase contacts accessing the increased number of planes. However, this approach is associated with increased density of the conductive lines that electrically couple the increased number of staircase contacts with the decoder. Such increased density introduces another set of manufacturing process challenges.
It is desirable to provide a structure for three-dimensional integrated circuit memory using a vertical channel structure that can decrease the trade-offs that come with increased memory capacity.